Pulse rate to analog converter

ABSTRACT

A system for providing an analog output signal whose average amplitude is proportional to the frequency of an input signal including a constant pulse width generator responsive to the input signal for providing a series of pulses each of which has a predetermined duration at the same frequency as the input signal and an averaging circuit responsive to the series of pulses for providing an analog signal whose average amplitude is a function of the duty cycle of the constant pulse width generator.

United States Patent [721 Inventors William R. Boyd Oakland; Robert C. Franklin. San Jose, both of, Calif. [21 1 Appl. No. 733,626 [22] Filed May31, 1968 145] Patented July 6, 1971 [73] Assignee Beckrnan instruments, Inc.

[54] PULSE RATE T0 ANALOG CONVERTER 2 Claims, 6 Drawing Figs.

[52] US. Cl 307/255, 307/233, 328/127, 307/247, 328/140 [51] int. Cl 03k 17/00, H03b 3/04 [50] Field of Search 328/140, 132, 151, 127, l, 5; 307/233, 246, 255

[56] Relerences Cited UNITED STATES PATENTS 2,429,072 10/1947 Place 328/132 2,574,551 11/1951 Ellison et a1. 328/127 2,630,529 3/1953 Mann et al 328/5 2,807,717 9/1957 Paulsen 328/1 2,924,712 2/1960 Edens... 328/1 3,444,393 5/1969 Sassler 328/127 Primary Examiner-Donald D. Forrer Assistant ExaminerHar0ld A. Dixon AnomeysRichard M. Jennings and Robert .1. Steinmeyer ABSTRACT: A system for providing an analog output signal whose average amplitude is proportional to the frequency of an input signal including a constant pulse width generator responsive to the input signal for providing a series of pulses each of which has a predetermined duration at the same frequency as the input signal and an averaging circuit responsive to the series of pulses for providing an analog signal whose average amplitude is a function of the duty cycle of the constant pulse width generator.

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INVENTORS WILLIAM R. BOYD ROBERT c. FRANKLIN AT roam PULSE RATE T ANALOG CONVERTER BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates in general to pulse rate to analog converters and more particularly to a system for continuously and accurately monitoring the speed of a rotational element, such as a centrifuge rotor, and providing an analog output signal whose average amplitude is a function of the rotational speed of the element.

2. Description of the Prior Art In many instances it is necessary to continuously monitor the speed of a rotational element. For example, in a centrifuge apparatus the speed ofthe centrifuge rotor must be accurately controlled not only to regulate the magnitude of the centrifugal force being generated but, also, to guard against the rotor exceeding its maximum speed rating and possibly disintegratmg.

In the past it has been common practice to monitor the rota tional speed of a centrifuge rotor by a conventional DC electric tachometer which is mechanically connected to the shaft upon which the rotor is mounted. The tachometer provides a DC signal whose amplitude is proportional to the speed of the rotor and whose polarity represents the direction of rotation. It has been found that such tachometers suffer from several serious drawbacks. First, the linearity of the output signal (amplitude v. r.p.m.) over the rotor speed range falls outside the desired operating tolerances. Secondly, the DC output signal derived from the tachometer is subject to unpredictable variations due to changes in the contact between the brushes and commutator surfaces of the tachometer. Finally, the highly magnetic environment which is associated with a drive motor of a centrifuge rotor adversely affects the performance of a conventional DC tachometer.

SUMMARY OF THE INVENTION In brief the present invention contemplates an electronic system for continuously and accurately monitoring the speed of a rotational element, such as the centrifuge rotor, by providing an analog signal whose average amplitude is proportional to the rotational speed of the element being monitored. To this end there is provided a suitable transducer for generating a train of pulses whose frequency is a function of the speed rotational element. A constant pulse width generator responds to the input pulse signal to provide a pulse train at the same frequency as the input signal, with each pulse in the train having a predetermined duration. An averaging circuit comprising a series connected resistor-capacitor network is coupled to the output of the constant pulse width generator by a switching circuit which responds to the train of constant width pulses to alternately connect the averaging circuit to a source of charging voltage for the duration of each pulse from the generator and to circuit ground during the absence of a pulse. The averaging circuit is thereby charged and discharged at the frequency rate of the train of constant width pulses to provide an analog output signal whose average amplitude is a function of the duty cycle of the pulse generator.

Accordingly the primary object of the present invention is an electronic system for converting a pulse rate input signal to an analog output signal whose average amplitude is a function of the frequency of the input signal.

Another object of the present invention is the provision ofa system for accurately and continuously monitoring the speed ofa rotational element.

A further object is the provision of an electronic speed monitoring system that provides a stable output signal which is substantially free from drift.

Still a further object is the provision of an electronic tachometer exhibiting optimum linearity (output signal v r.p.m.) throughout its dynamic range.

These and other objects and advantages of the' invention will become apparent following the detailed description when read in conjunction with the accompanying drawing in which:

BRIEF DESCRIPTION OF THE DRAWING FIG. 1 is a block diagram of the overall rotational speed monitoring system in accordance with the principles of the present invention;

FIG. 2 illustrates, partially in block diagram form and partially in schematic, the details of the pulse rate to analog converter;

FIG. 3 is a schematic diagram of a typical NOR circuit DETAILED DESCRIPTION OF THE INVENTION With reference now to the drawings and more particularly to FIG. I thereof, it will be observed that the reference numeral I0 designates a centrifuge rotor carried by a flexible shaft 11 to which is connected a circular disc 12. A suitable transducer 14 is associated with the disc for the purpose of deriving a signal having a frequencyfwhich varies as a function of the rotational speed of the shaft 11. It will be appreciated that the transducer may be either magnetically or optically coupled to the disc 12. The important feature is that the transducer provide an output signal whose frequency f is a function of the speed of the rotational shaft 11. In this connection it will also be understood that the pulse rate to analog signal converter of the present invention may be advantageously employed in connection with monitoring the speed of other rotational elements, or for that matter, any output signal whose frequency must be determined.

The output signal derived from transducer 14 is impressed upon the input of a frequency divider 15 by way of an amplifier I6 and a monostable or one-shot multivibrator 17. Oneshot multivibrator 17 serves to shape the input signal to provide a series of rectangular shaped pulses at the input of frequency divider 15. Although the time constant of one-shot multivibrator I7 is not critical, to avoid loss of information pulses, the switching period must be at least lessthan the maximum expected frequency of the input signal. Of course, it will be appreciated that other wave shaping elements may be employed, the particular design of which depends largely upon the nature of the output signal from the transducer 14. For example, if the signal is sinusoidal in nature, the wave shaping network may take the form of an overdriven class A amplifier or a conventional Schmitt trigger, each of which is capable of providing a rectangular pulse train output.

In frequency divider 15 the data rate or frequency of the input signal is reduced by a predetermined factor, the magnitude of which depends upon the initial frequency of the input signal. That is, generally speaking, the frequency divider consists of three parallel circuit channels, each of which is capable of dividing the frequency of the input signal by a different factor. To this end each channel may comprise a suitable binary counter wherein each counter has a different number of stages so as to divide the input signal by a different factor. A speed selector switch cooperates with the frequency divider to route the pulse input signal through the proper dividing channel. It will be appreciated that in many cases such data reduction is not necessary and the frequency dividing circuits may be omitted.

The series of pulses from frequency divider 15 are applied to the input of a pulse rate to analog converter designated generally by the reference numeral 20 and comprising a constant pulse width generator 21, a switching circuit 22, and an averaging circuit 23.

In general, the constant pulse width generator 21 responds to the pulse input signal to provide a series of pulses at the Referring now to FIG. 2, there is illustrated, partially in block diagram form and partially in schematic, the details of the pulse rate to analog converter. As may be readily seen from an inspection of thedrawing the series of pulses from frequency divider is AC coupled to the set input terminal (s) of a bistable multivibrator or flip-flop 24 by a capacitor 25. The signal output of flip-flop 24 is in turn connected to one input terminal of a NOR gate 26.

A crystal-controlled high frequencyoscillator 27 provides a stable high frequency pulse output which is simultaneously impressed upon the other input terminal of NOR gate 26 and one input terminal of NOR gate 28 by way of an inverter 29 which serves to isolate or unload the high frequency oscillator 27 from the remainder of the gating circuitry.

In the preferred embodiment frequency oscillator 27 provides a series of pulses at a frequency of l megahertz. However, it will be understood that the optimum reference frequency of the oscillator depends upon a number of factors including the expected frequency excursions or range of the input signal and, thus, other reference frequencies may be employed.

The output signal of NOR gate 26 is fed to a flip-flop 33 which includes two output lines 31 and 32, the latter terminal (32) being connected to a second'input terminal of NOR gate 28.

Pulses passed by NOR gate 28 are counted by means of a binary counter which generates a reset pulse after a predetermined number of pulses. In effect binary counter 34 divides the frequency of the pulse input signal by a predetermined factor which is governed by the number of stages in the counter. In the illustrated embodiment counter 34 comprises 12 stages to divide the input signal frequency by a factor of 2". This means that binary counter 34 generates one reset pulse for every 4096 input pulses or, stated another way, since the input pulse frequency is at l megahertz, a reset pulse is generated every 4096 microseconds which time period dictates the duration of the pulse generated by the constant pulse width generator in a manner to be presently described. In practice binary counter 34 may comprise a series of cascaded bistable elements, such as J-K flip-flops or magnetic cores having square hysteresis characteristics, and is commonly referred to as a ripple counter."

Switching circuit 23 includes a pair of transistors Q and 0;, connected in series between the positive side of a suitable power supply (not shown) and circuit ground by series connected current limiting resistors 50 and SI which limit the magnitude of the current flowing through transistors 0 and 0 during the on" and off transition periods. The base electrodes of both transistors Q and Q are connected to the output of constant pulse width generator transistor 0 by way of a transistor Q and transistor 0 by way of an inverter 52. Transistor O has its emitter electrode connected directly to circuit ground and its collector electrode connected to the side of the power supply by way of a voltage dividing network comprising resistors 53 and 54 including a junction point 55 which is connected to the base electrode of transistor 0 Transistors Q and Q respond to the constant width pulses appearing at terminal 31 to alternately couple an averaging circuit, designated generally by the reference numeral 23, between the positive side of the power supply and circuit ground in a manner to be presently described. Averaging cir cuit 23 comprises a resistor 56 and a capacitor 57 both of which are characterized by relatively large valves, say on the order of 5000 ohms for the resistor and 22 microfarads for the capacitor, so as to exhibit a relatively long time constant as compared to the time periods of the signal waveforms being operated on. In this manner capacitor 57 effectively integrates the pulse output of constant pulse width generator 21 and provides an analog output signal whose average amplitude is a function of the duty cycle of the constant pulse width generator at an output terminal 58.

Prior to describing the operation of the present invention, it is believed it would first be appropriate to discuss briefly a typical NOR circuit which may be used in the preferred embodiment. Referring to PK]. 3, a NOR gate is shown comprising a pair of NPN transistors Q, and Q each having its emitter electrode connected to circuit ground and its collector electrode connected to the positive (ri') side of an appropriate power supply (not shown) by way of a load resistor 40. The base electrodes of the transistors Q, and 0,, are connected to a pair of input terminals 41 and 42, respectively, by coupling resistors 43 and 44.

In operation when a positive input signal is impressed upon either one or both input terminals 411 and 42, its associated transistor is driven into saturation or turned on" thereby clamping the output terminal 45 to circuit ground through the low internal resistance of the transistor. Thus, upon the application of a positive input signal to one of the input terminals output terminal 45 falls from a positive voltage to a zero voltage (circuit ground). On the other hand, ifeither no signal or a negative signal is impressed upon both the input terminals 41 and 42, transistors Q, and 0 are turned off and a positive output signal appears at output terminal 45. In summary, the NOR gate provides a zero voltage output signal upon the occurrence of a positive input signal at one or both of its input terminals and a positive output signal in the absence of an input signal at both of its input terminals. Of course, it will be appreciated that the illustrated embodiment is only one of many NOR circuit configurations which may be employed in the present invention.

.To facilitate a complete understanding of the operation of the present invention reference will be made to FIG. 4 which graphically illustrates signal waveforms at various points throughout the preferred embodiment shown in FIG. 2.

At the outset the quiescent condition of the various components making up the pulse rate to analog converter will be described. In the absence of a pulse input signal at the input terminal 30, flip-flop 24 resides in its high state as depicted by the reference numeral so associated with the signal waveform (b) shown in FiG. 4. This positive signal causes the output terminal of NOR gate 26 to be at circuit ground or zero volts in the manner previously discussed in connection with the typical NOR circuit shown in FIG. 3, it follows that a positive signal from flip-flop 24 effectively inhibits or prevents NOR gate 26 from passing the high frequency pulse train provided by frequency oscillator 27. In other words, the high frequency pulses appearing at one input of NOR gate 26 have no effect on the output signal appearing at the output terminal because of the positive signal already appearing on the other input terminal and, thus, NOR gate 26 is effectively closed.

In its quiescent'state, the output line 32 of flip flop 33 resides in its high state (ri' signal) while its other output line 31 resides in its low state (zero volts) as represented by the waveforms (c) and (d), respectively, of FIG. 4. The positive signal appearing on line 32 effectively closes NOR gate 28 to prevent the reference frequency pulses appearing at the other input of NOR gate 28 from reaching the binary counter 34 in the same manner as described in connection with the operation of NOR gate 26. Finally, the zero volt signal appearing on output line 31 holds transistors Q, and O in a nonconductive state while simultaneously biasing transistor 0 into a conductive condition.

The first pulse 61 of an input pulse train arriving at terminal 30 (waveform (a), FIG. 4) triggers flip-flop 24, causing its output to fall to a low state (zero volts), as shown at 62 in waveform (b) of FIG. 4, thereby opening NOR gate 26 so that it passes the next I megahertz input pulse derived from frequency oscillator 27 to the set input(s) of flip-flop 33. This pulse triggers fiip-flop 33 causing the state of its output lines 31 and 32 to reverse. That is, line 32 falls to zero volts as shown at 63 of waveform while line 31 rises to a positive voltage as shown at 64 of waveform (d), thereby initiating the constant width pulse interval (T,). In passing, it should be noted that after the first reference pulse flip-flop 33 is insensi tive to the following pulses since these pulses are all like polarity signals.

The zero volt signal now appearing on line 32 opens NOR gate 28 to impress the l megahertz frequency pulse train upon the input of binary counter 34. Counter 1M generates a reset pulse 65 (waveform (2), FIG. 4) after 4096 input pulses which reset pulse is differentiated by an RC network 35 and fed to the reset input (r) of flip-flop 24 to restore the flip-flop to its original state as shown by reference numeral 66 of waveform (b). The positive going signal derived from flip-flop 24 is fed to the reset input (r) of flip-flop 33 to restore it to its original state as shown by reference numerals 67 and 68 of waveforms (0) nd (d), respectively, thereby terminating the constant width pulse interval (T,) and closing NOR gate 28 to prevent subsequent reference pulses from reaching the binary counter 34. It should be noted that NOR gate 26 and flip-flop 33 serve as a time buffer to ensure that the constant width pulse 70 always commences and terminates in synchronism with the frequency oscillator 27.

The above cycle is repeated for every input pulse appearing at input terminal 30. Thus, it will be apparent that there is provided on output line 31, a series of pulses 70 at the same frequency as the pulse input signal (waveform (a)) with each pulse 70 having a constant width or duration (T,).

The constant width pulses 70 derived from generator 21 are coupled to the base electrode of transistor 0 by resistor 59 driving transistor Q into saturation to complete an electrical circuit between the positive side of the power supply and circuit ground. Current then flows from the positive terminal to ground through resistors 53 and 54 causing the voltage at junction 55 to fall to a more negative value. This negativegoing voltage is coupled to the base electrode of transistor 0 biasing it into conduction to thereby couple capacitor 57 to the positive side of the power supply.

Simultaneously with being applied to transistor 0,, the pulse 70 after being inverted by inverter 52, is fed to transistor to drive it into cutoff which opens the circuit between junction point 37 and ground. Under these conditions capacitor 57 now charges toward the positive reference potential supplied by the power supply by way of the emitter-collector junction of transistor 0,, resistor 50, and resistor 56 as depicted by the solid arrow. This charging current flows for the duration of each pulse 70 provided by constant pulse width generator 21.

Upon the termination of a constant width pulse 70, transistor O is cutoff, opening the circuit between junction point 37 and the power supply while transistor O is driven into saturation to complete an electrical circuit between capacitor 57 and circuit ground. Capacitor 57 now discharges through ground by way of resistor 56, resistor 51, and the collector-emitter electrode path of transistor Q as depicted by the dotted arrow. At this point it should be noted that transistors Q and Q are well matched with regard to their collector-emitter saturation characteristics while resistors 50 and 51 are of equal value. This means that capacitor 57 charges and discharges through the same impedance path to provide an optimum linearity of output voltage vs. duty cycle throughout the dynamic range of the circuit.

From the above discussion it will be apparent that transistors 0 and Q respond to the pulse train provided by the constant pulse width generator 21 to alternately connect capacitor 57 between the side of the power supply and circuit ground. In this manner capacitor 57 is charged and discharged once each cycle of the constant pulse width generator 21 to provide at output terminal 58 an analog signal whose average amplitude is a function of the duty cycle of the pulse generator 21 as shown by the waveform'm of FIG. 4.

This latter concept may be best understood by comparison of the signal waveforms shown in FIGS. and 6. It will be re called that capacitor 57 charges during the duration (T,) of each input pulse 70 derived from constant pulse width generator 21 and discharges during the absence of a pulse output. Since the width or duration (T,) of each pulse provided by generator 21 is constant, the charging time interval of capacitor 57 is also constant. 0n the other hand, the discharging time period varies as a function of the frequency of constant width pulses 70. In other words, the relative charging and discharging time periods of the capacitor 57 is a function of the duty cycle of constant pulse width generator 21, wherein the duty cycle is defined by the ratio of the width or duration (1",) of each pulse 70 to the time period (T between pulses 70. Thus, as shown in waveform (a) of FIG. 5, an increase in the frequency of pulse output 70 increases the duty cycle of pulse generator 21. This means that capacitor 57 charges for a longer time period than it discharges,resulting in an analog output signal having a higher average amplitude (E,,,,, as shown in waveform (b) of FIG. 5.

Conversely, as illustrated in waveform (a) of FIG. 6, a decrease in the frequency of pulses 70 results in a lower duty cycle for pulse generator 21. This in turn means that capacitors 57 charging time period is less than its discharging time period, resulting in an analog output signal having a lower average amplitude (E as represented by the waveform (b) of FIG. 6.

It will be recalled that the frequency of the output pulse train 70 provided by pulse generator 21 is equal to the frequency of the input signal impressed upon input terminal 30. Consequently, the average amplitude of the analog output signal appearing at output terminal 38 is not only a function of the duty cycle of pulse generator 21, but is also proportional to one frequency of the original pulse input signal.

Numerous modifications and departures from the specific apparatus described herein may be made by those skilled in the art without departing from the inventive concept of the invention. For instance, the division factor provided by binary counter 34 is a matter of design governed by the frequency of the reference oscillator 27 and the expected frequency of the input signal and thus may be other than that specifically illustrated. Accordingly, the invention is to be construed as limited only by'the spirit and scope of the appended claims.

We claim:

1. A system for converting an input signal having a frequency (1) into an output signal whose average amplitude is a function of the frequency (f) of the input signal comprising:

constant pulse width generating means responsive to the input signal for providing a series of output pulses at the same frequency as the input signal, each pulse-having an equal and predetermined duration;

said constant pulse generating means comprising a high frequency oscillator for providing a series of reference pulses at a predetermined frequency, counting means and a bistable circuit, means including said bistable circuit and responsive to the input signal for coupling said reference pulses to said counting means and said bistable circuit, said bistable circuit responding to the first reference pulse to initiate a pulse output signal, said counting means providing an output signal after a predetermined number of reference pulses, and means for coupling said output signal to said bistable circuit to reset said bistable circuit to its original state to provide a pulse output signal having a predetermined duration;

a source of voltage;

an averaging circuit; and

switching means coupled to the output of said pulse generating means for connecting said source of voltage to said averaging circuit for the duration of each output pulse provided by the pulse generating means whereby the averaging circuit provides an analog. signal output having an average amplitude which is a function of the duty cycle of the pulse generating means.

2. A system as defined in claim 1 wherein:

said averaging circuit includes acapacitor;

means for connecting said capacitor to said resistance means;

and means for coupling the base electrodes of said first and second transistors to said pulse generating means, said transistors responding to the pulse output of said constant width pulse generating means to alternately couple the capacitor between the voltage source and circuit ground. 

1. A system for converting an input signal having a frequency (f) into an output signal whose average amplitude is a function of the frequency (f) of the input signal comprising: constant pulse width generating means responsive to the input signal for providing a series of output pulses at the same frequency as the input signal, each pulse having an equal and predetermined duration; said constant pulse generating means comprising a high frequency oscillator for providing a series of reference pulses at a predetermined frequency, counting means and a bistable circuit, means including said bistable circuit and responsive to the input signal for coupling said reference pulses to said counting means and said bistable circuit, said bistable circuit responding to the first reference pulse to initiate a pulse output signal, said counting means providing an output signal after a predetermined number of reference pulses, and means for coupling said output signal to said bistable circuit to reset said bistable circuit to its original state to provide a pulse output signal having a predetermined duration; a source of voltage; an averaging circuit; and switching means coupled to the output of said pulse generating means for connecting said source of voltage to said averaging circuit for the duration of each output pulse provided by the pulse generating means whereby the averaging circuit provides an analog signal output having an average amplitude which is a function of the duty cycle of the pulse generating means.
 2. A system as defined in claim 1 wherein: said averaging circuit includes a capacitor; said switching means comprises first and second transistors each having emitter, collector, and base electrodes, the emitter electrode of said first transistor being connected to the source of voltage and the emitter electrode of said second transistor being connected to circuit ground, resistance means connected between the collector electrodes of said transistors to thereby connect said first and second transistors in series between said voltage source and circuit ground; means for connecting said capacitor to said resistance means; and means for coupling the base electrodes of said first and second transistors to said pulse generating means, said transistors responding to the pulse output of said constant width pulse generating means to alternately couple the capacitor between the voltage source and circuit ground. 